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PAN301BSI-208
PAN301BSI-208 CMOS HIGH PERFORMANCE OPTICAL MOUSE SENSOR General Description
The PAN301BSI-208 is a high performance CMOS process optical mouse sensor with DSP integration chip that serves as a non-mechanical motion estimation engine for implementing a computer mouse. Features Single 3.3 volt power supply Precise optical motion estimation technology Complete 2-D motion sensor No mechanical parts Optical Lens 1:1 Accurate motion estimation over a wide range of System Clock 18.432 MHz surfaces High speed motion detection up to 37 inches/sec Speed and acceleration can be up to 20g High resolution up to 800cpi Power down pin and register setting for low power Resolution dissipation. Power saving mode during times of no movement Serial Interface for programming and data transfer I/O pin 5.0 volt tolerance Frame Rate Operating Current Package 37 inches/sec Power Supply Key Specification Wide operating supply range 3.0V~3.6V
Acceleration 20g 400/600/800cpi 3000 frames/sec 12mA @Mouse moving (Normal) 5mA @Mouse not moving (sleep1) 60uA @Power down mode Shrunk DIP20
Ordering Information Order number PAN301BSI-208 I/O CMOS output Resolution 800 cpi
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1. Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name VSS_LED LED OSCOUT OSCIN VDDD VSSD VSSA VDD VDDA VRT YA YB XA XB NC NC NC SCLK SDIO PD Type GND I/O OUT IN PWR GND GND PWR PWR BYPASS OUT OUT OUT OUT IN I/O IN Definition LED ground LED control Resonator output Resonator input Chip digital power, 3.0V Chip digital ground Chip analog ground Chip power, 3.3V power supply Chip analog power, 3.0V Analog voltage reference YA quadrature output YB quadrature output XA quadrature output XB quadrature output No connection No connection No connection Serial interface clock Serial interface bi-direction data Power down pin, active high
1
20
LB
RB
+Y
1
20
10
11
10
11
+X
Figure 1. Top view pinout Figure 2. Top view of mouse
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2. Block Diagram and Operation
LED VSS_LED LED DRIVE POWER ON RESET VOLTAGE REGULATOR AND POWER CONTROL CMOS IMAGE SENSOR QUADRATURE OUTPUT QUADRATURE OUTPUTS XA XB YA YB
VDD VDDD VDDA VSSD VSSA
3.3V POWER
PD VRT
DIGITAL SIGNAL PROCESSOR
SERIAL INTERFACE
SCLK SDIO
SERIAL INTERFACE
CONTROL REGISTER
OSCILLATOR
OSCIN OSCOUT
RESONATOR
Figure 3. Block diagram The PAN301BSI-208 is a high performance CMOS-process optical mouse sensor with DSP integration chip that serves as a non-mechanical motion estimation engine for implementing a computer mouse. It is based on new optical navigation technology, which measures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. The sensor is in a 20pin optical package. The output format is two-channel quadrature (X and Y direction), which emulates encoder phototransistors. The current X and Y information are also available in registers accessed via a serial port.
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3. Registers and Operation
The PAN301BSI-208 can be programmed through registers, via the serial port, and DSP configuration and motion data can be read from these registers. All registers not listed are reserved, and should never be written by firmware.
3.1 Registers
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 Name Product_ID Product_ID Motion_Status Delta_X Delta_Y Operation_Mode Configuration Image_Quality R/W R R R R R R/W R/W R Default 0x30 0x1N Data Type Eight bits [11:4] number with the product identifier Four bits [3:0] number with the product identifier Reserved [3:0] number is reserved for future Bit field Eight bits 2's complement number Eight bits 2's complement number Bit field Bit field Eight bits unsigned integer
3.2 Register Descriptions
0x00 Bit Field Usage 0x01 Bit Field Usage 7 6 PID[3:0] 5 7 6 5 Product_ID 4 PID[11:4] The value in this register can't change. It can be used to verify that the serial communications link is OK. Product_ID 4 3 2 1 0 Reserved [3:0] 3 2 1 0
The value in this register can't change. PID[3:0] can be used to verify that the serial communications link is OK. Reserved [3:0] is a value between 0x0 and 0xF, it can't be used to verify that the serial communications.
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0x02 Bit Field Usage 7 Motion 6 5 Reserved[6:5] Motion_Status 4 DYOVF 3 DXOVF 2 RES[2:1] 1 0 Reserved
CMOS Optical Mouse Sensor
Register 0x02 allows the user to determine if motion has occurred since the last time it was read. If so, then the user should read registers 0x03 and 0x04 to get the accumulated motion. It also tells if the motion buffers have overflowed since the last reading. The current resolution is also shown. Reading this register freezes the Delta_X and Delta_Y register values. Read this register before reading the Delta_X and Delta_Y registers. If Delta_X and Delta_Y are not read before the motion register is read a second time, the data in Delta_X and Delta_Y will be lost.
Notes
Field Name
Description Motion since last report or PD 0 = No motion (Default) 1 = Motion occurred, data ready for reading in Delta_X and Delta_Y registers
Motion
Reserved[6:5] DYOVF
Reserved for future Motion Delta Y overflow, Y buffer has overflowed since last report 0 = No overflow (Default) 1 = Overflow has occurred Motion Delta X overflow, X buffer has overflowed since last report
DXOVF
0 = No overflow (Default) 1 = Overflow has occurred Resolution in counts per inch 0 = 800 (Default) 1 = 400 2 = 600
RES[2:1]
Reserved
Reserved for future
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0x03 Bit Field Usage 0x04 Bit Field Usage 7 Y7 6 Y6 5 Y5 4 Y4 7 X7 6 X6 5 X5 4 X4 Delta_X 3 X3 2 X2 1 X1 0 X0
CMOS Optical Mouse Sensor
X movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Report range -128~+127. Delta_Y 3 Y3 2 Y2 1 Y1 0 Y0
Y movement is counts since last report. Absolute value is determined by resolution. Reading clears the register. Report range -128~+127.
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0x05 Bit Field Usage 7 6 5 Operation_Mode 4 3 2 1 0 LEDsht_enh XY_enh Reserved Slp_enh Slp2au Slp2mu Slp1mu Wakeup Register 0x05 allows the user to change the operation of the sensor. Shown below are the bits, their default values, and optional values. Operation_Mode[4:0] "0xxxx"=Disable sleep mode "10xxx"=Enable sleep mode1 "11xxx"=Enable sleep mode2 "1x100"=Force enter sleep23 "1x010"=Force enter sleep13 "1x001"=Force wakeup from sleep mode3 Notes: 1. Enable sleep mode, but disable automatic entering sleep2 mode, that is, only 2 modes will be used, normal mode and sleep1 mode. After 1 sec not moving during normal mode, the chip will enter sleep1 mode, and keep on sleep1 mode until moving is detected or wakeup is asserted. 2. Enable sleep mode full function, that is 3 modes will be used, normal mode, sleep1 mode and sleep2 mode. After 1 sec not moving during normal mode, chip will enter sleep1 mode, and keep on sleep1 mode until moving is detected or wakeup is asserted. And after 60 sec not moving during sleep1 mode, the chip will enter sleep2 mode, and keep on sleep2 mode until detect moving or force wakeup to normal mode. Mode Sampling rate @3000frame/sec Active duty cycle @3000frame/sec Sleep1 94/sec 22% Sleep2 3/sec 2.24% 3. Only one of these three bits slp2mu_enh, slp1mu_enh, and wakeup can be set to 1 at the same time, others have to be set to 0. After a period of time, the bits, which was set to 1, will be reset to 0 by internal signal. Notes Field Name LEDsht_enh XY_enh Reserved Slp_enh Slp2au Slp2mu Slp1mu Wakeup Description LED shutter enable / disable 0 = Disable 1 = Enable (Default) XY quadrature output enable/disable 0 = Disable 1 = Enable (Default) Reserved for future Sleep mode enable/disable 0 = Disable 1 = Enable (Default) Automatic enter sleep2 mode enable/disable 0 = Disable (Default) 1 = Enable Manual enter sleep2 mode, set "1" will enter sleep2 and this bit will be reset to "0" Manual enter sleep1 mode, set "1" will enter sleep2 and this bit will be reset to "0" Manual wake up from sleep mode, set "1" will enter wakeup and this bit will be reset to "0" 7 V1.1, MAY. 2004
CMOS Optical Mouse Sensor
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0x06 Bit Field Usage Notes 7 6 5 Reserved[7:4] Configuration 4 3 PD 2 RES[2:1] 1 0 Reserved
CMOS Optical Mouse Sensor
The Configuration register allows the user to change the configuration of the sensor. Shown below are the bits, their default values, and optional values. Field Name Reserved[7:4] Description Reserved for future Power down mode PD 0 = Normal operation (Default) 1 = Power down mode Output resolution setting RES[2:1] 0 = 800 (Default) 1 = 400 2 = 600 Reserved Reserved for future Image_Quality 7 6 5 4 Imgqa[7:0] Image Quality is a quality level of the sensor in the current frame. Report range 0~255. The minimum level for normally working is 45. Field Name Imgqa[4:0] Description Image quality report range: 0(worst) ~ 255(best). 3 2 1 0
0x07 Bit Field Usage Notes
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4. Specifications
Absolute Maximum Ratings Symbol TSTG TA Parameter Storage temperature Operating Temperature Lead Solder Temp VDD ESD VIN DC input voltage -0.5 DC supply voltage -0.5 Min -40 -15 Max 85 55 260 4.0 2 5.5 Unit C C V kV V All pins, human body model MIL 883 Method 3015 PD, SDIO, SCLK, XA, XB, YA, YB,VDD For 10 seconds, 1.6mm below seating plane. Notes
Recommend Operating Condition Symbol TA VDD VN FCLK FR SCLK Z S A R Parameter Operating Temperature Power supply voltage Supply noise Clock Frequency Frame Rate Serial Port Clock Frequency Distance from lens reference plane to surface Speed Acceleration Resolution 400 2.3 0 2.4 18 12.000 1953 18.432 3000 Min. 0 3.3 3.0 Typ. Max. 40 3.6 3.6 100 24.576 4000 10 2.5 37 20 800 Unit C V V mV MHz Frames/s MHz mm Inches/sec g cpi Refer to Figure 4. Peak to peak within 0-100 MHz Set by crystal or ceramic resonator. 1953 frames/s @ FCLK=12.000MHz 4000 frames/s @ FCLK=24.567MHz Notes
VDDD, VDDA Power supply voltage
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Package Lid Lens
Z OBJECT SURFACE
Figure 4. Distance from Lens Reference Plane to Surface
+X +Y
ESD LENS RING
BASE PLATE
PLASTIC SPRING
CLIP
LED
SURFACE IS 0 REF. PCB SENSOR BASE PLATE ALIGNMENT POST
Unit: mm
Figure 5. 2D assembly
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AC Operating Condition Electrical Characteristics over recommended operating conditions. Typical values at 25 C, VDD =3.3 V, FCLK=18.432MHz Symbol tPD tPDW tPDR Parameter Power Down PD Pulse Width PD Pulse Register 700 333 Min. Typ. Max. Unit 500 us us us Notes From PD. (Refer to Figure 15) Pulse width to reset the serial interface. (Refer to Figure 15) One frame time maximum after setting bit 2 in the Configuration register @3000frame/sec. (Refer to Figure 17)
CMOS Optical Mouse Sensor
tPUPD
Power Up from PD
9
30.5
From PD to valid quad signals. After tPUPD, all registers contain valid data from first image after PD. Note that an additional 90 ms frames for Auto-Exposure (AE) stabilization may be required if mouse movement occurred while PD was high. (Refer to Figure 15) ms us us From VDD to valid quad signals. 500usec + 90frames. Minimum hold time for valid data. (Refer to Figure 11) @3000frame/sec (Refer to Figure 14)
tPU tHOLD tRESYNC tSIWTT tr,tf tr,tf tr,tf
Power Up from VDD SDIO read hold time Serial Interface RESYNC. Serial Interface Watchdog Timer Timeout Rise and Fall Times: SDIO Rise and Fall Times: XA, XB, YA, YB Rise and Fall Times: ILED
15 3 1 1.7 25, 20 25, 20 10, 10
30.5
ms @3000frame/sec (Refer to Figure 14) ns ns ns CL = 30pf CL = 30pf LED bin grade: R; R1=100ohm
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DC Electrical Characteristics Electrical Characteristics over recommended operating conditions. Typical values at 25 C, VDD =3.3V Symbol Type: PWR IDD IDD IDDPD Supply Current Mouse moving (Normal) Supply Current Mouse not moving (sleep1) Supply Current (Power Down) Input voltage HIGH Input voltage LOW Output voltage HIGH Output voltage LOW Input voltage HIGH Input voltage LOW Output voltage LOW Output voltage HIGH Output voltage LOW 2.4 0.6 2.0 0.7 150 2.4 0.6 2.0 0.7 V V V V V @I OH = 2mA (SDIO only) @I OL = 2mA (SDIO only) When driving from an external source When driving from an external source 12 5 60 mA XA, XB, YA, YB, SCLK, SDIO = no load mA uA PD, SCLK, SDIO = high Parameter Min. Typ. Max. Unit
Type: SCLK, SDIO, PD VIH VIL VOH VOL VIH VIL VOL VOH VOL
Type: OSCIN
Type: LED mV @I OL = 25mA V V @I OH = 2mA @I OL = 2mA Type: XA, XB, YA, YB
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5. Quadrature Mode
The quadrature state of the PAN301BSI-208 tells mouse controller which direction the mouse is moving in. The output format is two channels quadrature (X and Y direction), which emulates encoder phototransistors. The DSP generates the x and y relative displacement values that are converted into two channel quadrature signals. The following diagrams show the timing for positive X motion, to the right or positive Y motion, up.
5.1 Quadrature Output Timing
X motion to the right Y motion up XA/YA
FOUR
XB/YB
83.3us
83.3us
83.3us
83.3us
XA/YA
THREE
XB/YB
83.3us
83.3us
166.7us
XA/YA
TWO
XB/YB
83.3us
250us
XA/YA
ONE
XB/YB
333.3us
333.3us @ 3000frames/second
Figure 6. Quadrature output timing
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5.2 Quadrature Output State Machine
The following state machine shows the states of the quadrature output pins. The three things to note are that state 0 is entered after a power on reset. While the PD pin is asserted, the state machine is halted. Once PD is de-asserted, the state machine picks up from where it left off. During times of mouse no movement will entry power saving mode, until mouse was moved.
PD POWER ON RESET STATE 0 (0,0)
CT IO N + T EC IR D
IR E D
IO N
T EC IR -D
N IO
-D IR EC T
+
X/Y output STATE XA/YA XB/YB 0 PD 1 2 3 0 1 1 1 1 0 0 0
N IO
PD
STATE 1 (0,1)
TI O N
STATE 3 (1,0)
-D IR EC
-D E IR
STATE 2 (1,1) PD
Figure 7. State machine
5.3 Quadrature Output Waveform
The following diagrams show the waveform of the two channel quadrature outputs. If the X, Y is motionless, the (XA, XB), (YA, YB) will keep in final state. Each state change (ex. STATE2 STATE3) is one count.
XA/YA X MOTION TO THE RIGHT Y MOTION UP ( + DIRECTION )
XB/YB STATE3 (1,0) STATE0 (0,0) STATE1 (0,1) STATE2 (1,1) STATE3 (1,0) STATE0 (0,0)
+1
+1
+
+1
D IR E
CT IO N
+ EC IR D
IO CT N
N O TI
+1
+1
MOTION COUNT
XA/YA
X MOTION TO THE LEFT Y MOTION DOWN ( - DIRECTION )
XB/YB STATE1 (0,1) STATE0 (0,0) STATE3 (1,0) STATE2 (1,1) STATE1 (0,1) STATE0 (0,0)
-1
-1
-1
-1
-1
MOTION COUNT
Figure 8. Quadrature output waveform
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6. Serial Interface
The synchronous serial port is used to set and read parameters in the PAN301BSI-208, and can be used to read out the motion information instead of the quadrature data pins. SCLK: The serial clock line. It is always generated by the host micro-controller. SDIO: The serial data line used for write and read data. PD: A third line is sometimes involved. PD(Power Down pin) is usually used to place the PAN301BSI-208 in a low power mode to meet USB suspend specification. PD can also be used to force re-synchronization between the micro-controller and the PAN301BSI-208 in case of an error.
6.1 Transmission Protocol
The transmission protocol is a two-wire link, half duplex protocol between the micro-controller and PAN301BSI-208. All data changes on SDIO are initiated by the falling edge on SCLK. The host microcontroller always initiates communication; the PAN301BSI-208 never initiates data transfers. The transmission protocol consists of the two operation modes: - Write Operation. - Read Operation. Both of the two operation modes consist of two bytes. The first byte contains the address (seven bits) and has a bit7 as its MSB to indicate data direction. The second byte contains the data.
FIRST BYTE R /W (1 BIT) ADDRESS (7 BIT) SECOND BYTE DATA (8 BIT)
MSB
LSB
MSB
LSB
Figure 9. Transmission protocol
6.1.1 Write Operation
A write operation, which means that data is going from the micro-controller to the PAN301BSI-208, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address (seven bits) and has a "1" as its MSB to indicate data direction. The second byte contains the data. The transfer is synchronized by SCLK. The micro-controller changes SDIO on falling edges of SCLK. The PAN301BSI-208 reads SDIO on rising edges of SCLK.
SCLK SDIO
DON'T CARE
1 1
2 A6
3 A5
4 A4
5 A3
6 A2
7 A1
8 A0
9 D7
10 D6
11 D5
12 D4
13 D3
14 D2
15 D1
16 D0
DON'T CARE
SDIO driven by Micro-controller
Figure 10. Write operation
6.1.2 Read Operation
A read operation, which means that data is going from the PAN301BSI-208 to the micro-controller, is always initiated by the micro-controller and consists of two bytes. The first byte contains the address, is written by the micro-controller, and has a "0" as its MSB to indicate data direction. The second byte contains the data and is driven by the PAN301BSI-208. The transfer is synchronized by SCLK. SDIO is
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changed on falling edges of SCLK and read on every rising edge of SCLK. The micro-controller must go to a high Z state after the last address data bit. The PAN301BSI-208 will go to the high Z state after the last data bit.
SCLK SDIO
DON'T CARE
1 0
2 A6
3 A5
4 A4
5 A3
6 A2
7
8
Hi-z
9 D7
10 D6
11 D5
12 D4
13 D3
14 D2
15 D1
16 D0
Hi-z R/W bit of next address
A1 A0
SDIO driven by Micro-controller Note "A"
SDIO driven by PAN301BSI-208 Note "B"
Note "A"
SCLK SDIO
1. Micro-controller send address to PAN301BSI-208. 2. Micro-controller release and set SDIO to Hi-Z after the last address bit. 7 A1 A0 tHOLD 3us,min 8 Hi-Z 9 D7
Note "B"
1. PAN301BSI-208 send data to Micro-controller . 2. PAN301BSI-208 release and set SDIO to Hi-Z after the last data bit. 16 Hi-Z D0
SCLK SDIO
1 R/W bit of next address SDIO driven by micro-controller
Figure 11. Read operation
6.2 Re-Synchronous Serial Interface
There are times when the SDIO line from the PAN301BSI-208 should be in the Hi-Z state. If the microprocessor has completed a write to the PAN301BSI-208, the SDIO line is Hi-Z, since the SDIO pin is still configured as an input. However, if the last operation from the microprocessor was a read, the PAN301BSI-208 will hold the D0 state on SDIO until a rising edge of SCLK. To place the SDIO pin into the Hi-Z state, first raise the PD line, and then toggle the SCLK line from high to low to high. The SDIO line will now be in the Hi-Z state. The PAN301BSI-208 and the micro-controller might get out of synchronization due to following condition.
PD SCLK SDIO Hi-Z 1us,min
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6
ADDRESS(R/W)
DATA
Figure 12. Forcing PAN301BSI-208 SDIO line to the Hi-Z state
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6.2.1 USB Suspend
Termination of a transmission by the micro-controller may sometimes be required (for example, due to a USB suspend interrupt during a read operation). To accomplish this the micro-controller should raise PD. The PAN301BSI-208 will not write to any register and will reset the serial port (but nothing else) and be prepared for the beginning of future transmissions after PD goes low.
6.2.2 Firmware Flaws Error, or Others Error
The PAN301BSI-208 and the micro-controller might get out of synchronization due to micro-controller firmware flaws. The PD pin can stay high, with the PAN301BSI-208 in the shutdown state, or the PD pin can be lowered, returning the PAN301BSI-208 to normal operation. If the microprocessor and the PAN301BSI-208 get out of sync, then the data either written or read from the registers will be incorrect. In such a case, an easy way to solve this is to raise PD to re-sync the parts after an incorrect read. The PAN301BSI-208 will reset the serial port but will not reset the registers and be prepared for the beginning of a new transmission.
6.2.3 Power On Problem
The problem occurs if the PAN301BSI-208 powers up before the microprocessor sets the SCLK and SDIO lines to be output.
6.2.4 ESD Events
The PAN301BSI-208 and the micro-controller might get out of synchronization due to ESD events. If the PAN301BSI-208 and the micro-controller might get out of synchronization due to power on problem or ESD events. An easy way to solve this is to soft reset the PAN301BSI-208.
VDD PD SCLK SDIO Hi-Z
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1us,min
ADDRESS(R/W)
DATA
Figure 13. Soft reset the PAN301BSI-208 (Reset full chip and SDIO line set to Hi-Z state)
6.3 Collision Detection on SDIO
The only time that the PAN301BSI-208 drives the SDIO line is during a READ operation. To avoid data collisions, the micro-controller should release SDIO before the falling edge of SCLK after the last address bit. The PAN301BSI-208 begins to drive SDIO after the next falling edge of SCLK. The PAN301BSI208 release SDIO of the rising SCLK edge after the last data bit. The micro-controller can begin driving SDIO any time after that. In order to maintain low power consumption in normal operation or when the PD pin is pulled high, the micro-controller should not leave SDIO floating until the next transmission (although that will not cause any communication difficulties).
6.4 Serial Interface Watchdog Timer Timeout
When there are only two pins to read register from PAN301BSI-208, and PD pin can't be used to resynchronous function. If the microprocessor and the PAN301BSI-208 get out of sync, then the data either written or read from the registers will be incorrect. In such a case, an easy way to solve this condition is to toggle the SCLK line from high to low to high and wait at least tSIWTT to re-sync the parts after an incorrect read. The PAN301BSI-208 will reset the serial port but will not reset the registers and be prepared for the beginning of a new transmission.
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tSIWTT SCLK tRESYNC 1us, min SDIO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CMOS Optical Mouse Sensor
Hi-Z
ADDRESS(R/W) DATA
Figure 14. Re-synchronous serial interface using watchdog timer timeout
6.5 Power Down Mode
There are two different ways to entry power down mode, using the PD line or register setting.
6.5.1 PD Line Power Down Mode
To place the PAN301BSI-208 in a low power mode to meet USB suspend specification, raise the PD line at least 700us. Then PD line can stay high, with the PAN301BSI-208 in the shutdown state, or the PD pin can be lowered, returning the PAN301BSI-208 to normal operation.
PD IDD tPD 500us
tPDW 700us,min
500us
90frames tPUPD 30.5ms
Figure 15. Power down minimum pulse width
PD SCLK SDIO
tPDW 700us,min
1 2 3 4 5 6 7 89 1 0 1 1 1 2 1 3 1 4 11 56
Hi-Z
ADDRESS(R/W)
DATA
Figure 16. PD line power down mode
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6.5.2 Register Power Down Mode
PAN301BSI-208 can be placed in a power-down mode by setting bit 3 in the configuration register via a serial port write operation. After setting the configuration register, wait at least 1frame times. To get the chip out of the power-down mode, clear bit 3 in the configuration register via a serial port write operation. In power-down mode, the serial interface watchdog timer is not available. But, The serial interface still can read/write normally. For an accurate report after leave power down mode, wait about 3ms before the micro-controller is able to issue any write/read operation to the PAN301BSI-208.
SCLK
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
Address=0x06
1 0 0 0 0 1 1 0 0 0
Data=0x08
0 0 1 0 0 0
1 frame, max
SDIO IDD
DATA
tPDR
Figure 17. Power-down configuration register writing operation
6.6 Error Detection
1.The micro-controller can verify success of write operations by issuing a read command to the same address and comparing written data to read data. 2. The micro-controller can verify the synchronization of the serial port by periodically reading the product ID register.
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7. Referencing Application Circuit for Cordless Optical Mouse 7.1 27MHz RF TX Circuit with Internal Regulator
PIN8 *Step-up DC/DC converter circuit
BATTERY L1 150uH D1 1N5819 POWER_3.3V
U1 C1 47uF R15 0 DGND
AIC1642-33CX 2 C2 100uF L2
3
1
GND
SW
VOUT
3.3uH AGND BATTERY
*RF Circuit
R2 C3 0.1uF
10 C4 0.1UF C5 1UF
RF_EN C6 0.1UF R3 27K X1 13.5225MHz R4 36K 2 C10 3 27pF Q3 3904 1 C12 27pF R6 36K C14 33pF R8 2K 1 1 R7 10K 3 C7 0.1UF Q1 3904 C11 100pF 2 3904 R5 56K 3 C8 10pF
L3 3.3uH
Q2
C9 C13
RF_DATA
2
*MCU
POWER_3.3V R9 30K C17 0.1uF ID_SYNC WHEEL_EN RESET Z1 Z2 R_KEY M_KEY 1 2 3 4 5 6 7 8 9 U2 P52 P53 TCC /RESET VSS P60./INT P61 P62 P63 EM78P156 DGND POWER_3.3V R11 20K ID_SYNC DGND S1 1 LB1 1 MB1 1 RB1 1 P51 P50 OSCI OSCO VDD P67 P66 P65 P64 18 17 16 15 14 13 12 11 10 RF_EN RF_DATA OSCI OSCO SCLK SDIO PD L_KEY C18 0.1uF DGND X2
C15 15pF
4MHz C16 15pF DGND POWER_3.3V
POWER_3.3V
2
L_KEY R13 Z1
R10 100K
R12 100K R14 10K C20 0.1uF DGND Z2
2
M_KEY
C19 0.1uF DGND ENSW1
10K
2
R_KEY
2
Z1 WHEEL_EN 3 COM Z2 ENCODER
2 1
DGND
*SENSOR
U3 1 DGND LED 3 X3 18.432MHz 4 5 C21 6 47uF DGND DGND AGND 8 C22 + 10uF 0.1uF C24 47uF AGND AGND C26 C23 9 10 VDD VDDA VRT XA YB YA 13 12 11 7 VSSD VSSA NC XB 15 14 2 20 19 18 17 16 PD SDIO SCLK
POWER_3.3V
R1
D2
VSS_LED LED OSCOUT OSCIN VDDD
PD SDIO SCLK NC NC
0.1uF
PAN301BSI-208
Figure 18. 27MHz RF transceiver circuit with internal regulator
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PixArt Imaging Inc. PAN301BSI-208 CMOS Optical Mouse Sensor
7.2 27MHz RF TX Circuit with Internal Regulator for Low Power Down Current
PIN8 *Step-up DC/DC converter circuit
BATTERY L1 150uH D1 1N5819 POWER_3.3V
U1 C1 47uF R15 0 DGND
AIC1642-33CX 2 C2 100uF L2
3
1
GND
SW
VOUT
3.3uH AGND BATTERY
*RF Circuit
R2 C3 0.1uF
10 C4 0.1UF C5 1UF
RF_EN C6 27K 13.5225MHz 36K 2 C10 3 27pF Q3 3904 1 C12 27pF R6 36K C14 33pF R8 2K 1 1 R7 10K 3 0.1UF R3 X1 R4 C7 0.1UF R5 Q1 3904 C11 100pF 2 3904 56K 3 C8 10pF
L3 3.3uH
Q2
C9 C13
RF_DATA
2
*MCU
POWER_3.3V R9 30K C17 0.1uF ID_SYNC PWR_EN RESET Z1 Z2 R_KEY M_KEY 1 2 3 4 5 6 7 8 9 U2 P52 P53 TCC /RESET VSS P60./INT P61 P62 P63 EM78P156 DGND POWER_3V R11 20K ID_SYNC RB1 1 2 DGND S1 1 DGND ENSW1 Z1 3 DGND DGND COM Z2 ENCODER 2 1 2 R_KEY MB1 1 2 M_KEY Z1 C19 0.1uF 10K LB1 1 P51 P50 OSCI OSCO VDD P67 P66 P65 P64 18 17 16 15 14 13 12 11 10 RF_EN RF_DATA OSCI OSCO SCLK SDIO PD L_KEY C18 0.1uF DGND X2
C15 15pF
4MHz C16 15pF POWER_3.3V
DGND
POWER_3V
2
L_KEY R13
R10 100K
R12 100K R14 Z2 10K C20 0.1uF DGND
*SENSOR
POWER_3V 3 Q4 P MOS R1 2 LED 3 X3 18.432MHz 4 5 C21 6 47uF DGND AGND C22 + 10uF 0.1uF C24 C26 47uF AGND AGND 0.1uF PAN301BSI-204 C23 9 10 VDDA VRT YB YA 12 11 DGND 7 8 VSSA VDD XB XA 14 13 VSSD NC 15 D2 DGND 1 2 VSS_LED LED OSCOUT OSCIN VDDD PD SDIO SCLK NC NC 20 19 18 17 16 U3 PD SDIO SCLK
PWR_EN
1
Figure 19. 27MHz RF TX circuit with internal regulator for low power down current
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7.3 27MHz RF TX Circuit Bypass Internal Regulator
*Step-up DC/DC converter circuit
BATTERY L1 150uH D1 1N5819 POWER_3V
U1 C1 3 47uF R15 0 DGND
AIC1642-33CX C2 GND 2 100uF L2
SW
VOUT
1
3.3uH AGND BATTERY R2 C3 0.1uF 10 C4 0.1UF C5 1UF
*RF Circuit
RF_EN C6 27K 13.5225MHz 36K 2 C10 3 1 27pF Q3 3904 1 C12 27pF R6 36K C14 33pF R8 2K 1 C11 100pF 2 3904 R7 10K 3 0.1UF R3 X1 R4 C7 0.1UF R5 Q1 3904 56K C8 10pF 3
L3 3.3uH
Q2
C9 C13
RF_DATA
2
*MCU
POWER_3V R9 30K C17 0.1uF Z1 Z2 R_KEY M_KEY ID_SYNC WHEEL_EN 1 2 3 4 5 6 7 8 9 U2 P52 P53 TCC /RESET VSS P60./INT P61 P62 P63 EM78P156 DGND DGND P51 P50 OSCI OSCO VDD P67 P66 P65 P64 18 17 16 15 14 13 12 11 10 RF_EN RF_DATA OSCI OSCO SCLK SDIO PD L_KEY C18 0.1uF X2
C15 15pF
4MHz C16 15pF POWER_3V
DGND
POWER_3V
POWER_3V R11 20K ID_SYNC DGND S1 1
LB1 1 MB1 1 RB1 1
2
L_KEY R13 Z1
R10 100K
R12 100K R14 Z2 10K C20 0.1uF DGND
2
M_KEY
C19 0.1uF DGND ENSW1
10K
2
R_KEY
2
Z1 WHEEL_EN 3 COM Z2
2 1
DGND
ENCODER
*SENSOR
U3 POWER_3V R1 D2 LED 3 X3 18.432MHz 4 5 C21 + 10uF 0.1uF DGND AGND 8 AGND 9 10 C24 0.1uF AGND PAN301BSI-208 VDD VDDA VRT XA YB YA 13 12 11 C22 6 7 VSSD VSSA NC XB 15 14 DGND 2 LED OSCOUT OSCIN VDDD SDIO SCLK NC NC 19 18 17 16 1 20 PD SDIO SCLK
VSS_LED
PD
Figure 20. 27MHz RF transceiver circuit bypass internal regulator
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PixArt Imaging Inc. PAN301BSI-208 CMOS Optical Mouse Sensor
7.4 27MHz RF TX Circuit Bypass Internal Regulator for Low Power Down Current
*Step-up DC/DC converter circuit
BATTERY L1 150uH D1 1N5819 POWER_3V
U1 C1 3 47uF R15 0 DGND
AIC1642-33CX C2 GND 2 100uF L2
SW
VOUT
1
3.3uH AGND BATTERY R2 C3 0.1uF 10 C4 0.1UF C5 1UF
*RF Circuit
RF_EN C6 27K 13.5225MHz 36K 2 C10 3 1 27pF Q3 3904 1 C12 27pF R6 36K C14 33pF R8 2K 1 C11 100pF 2 3904 R7 10K 3 0.1UF R3 X1 R4 C7 0.1UF R5 Q1 3904 56K C8 10pF 3
L3 3.3uH
Q2
C9 C13
RF_DATA
2
*MCU
POWER_3V R9 30K C17 0.1uF Z1 Z2 R_KEY M_KEY ID_SYNC PWR_EN 1 2 3 4 5 6 7 8 9 U2 P52 P53 TCC /RESET VSS P60./INT P61 P62 P63 EM78P156 DGND DGND P51 P50 OSCI OSCO VDD P67 P66 P65 P64 18 17 16 15 14 13 12 11 10 RF_EN RF_DATA OSCI OSCO SCLK SDIO PD L_KEY C18 0.1uF X2
C15 15pF
4MHz C16 15pF POWER_3V
DGND
POWER_3V
POWER_3V R11 20K ID_SYNC DGND S1 1
LB1 1 MB1 1 RB1 1
2
L_KEY R13 Z1
R10 100K
R12 100K R14 Z2 10K C20 0.1uF DGND
2
M_KEY
C19 0.1uF DGND ENSW1
10K
2
R_KEY
2
Z1 3 COM Z2
2 1
DGND DGND
ENCODER
*SENSOR
POWER_3V 3 Q4 P MOS 2 R1 D2 LED 3 X3 18.432MHz 4 5 C21 + 10uF 0.1uF DGND AGND 8 AGND 9 10 C24 0.1uF AGND PAN301BSI-208 VDD VDDA VRT XA YB YA 13 12 11 C22 6 7 VSSD VSSA NC XB 15 14 DGND 2 LED OSCOUT OSCIN VDDD SDIO SCLK NC NC 19 18 17 16 U3 1 20 PD SDIO SCLK
PWR_EN
1
VSS_LED
PD
Figure 21. 27MHz RF TX circuit bypass internal regulator for low power down current
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7.5 Typical Application for RF Receiver Circuit
VCC_5V Q1 PNP_2N3906 1 3 VCCD R2A1 VCCA
100 + C1 2 R1 4.7K SUSPEND DGND VCC_5V R2 470 RF_DATA D1 1 1 S1 DGND LED-DIP 2 2 LED1 ID_SYNC SUSPEND 1 2 3 4 5 14 1uF R2B1 0 C3 0.1uF +
C2 10uF
AGND C4 0.1uF U1 11 13 12 8 7 6 18 17 16 15 10 SCL SDA DGND 1 2 3 R3 1.3K DGND + 10uF DGND VCC_5V VCC_5V D+/SCLK D-/SDATA GND C5
JP1 1 2 3 4 HEADER 4
P0.0 P0.1 P0.2 P0.3 P1.0 P1.1
VCC D+/SCLK D-/SDATA VREG VPP VSS P0.4 P0.5 P0.6 P0.7
DGND U2 SCL GND SDA 24LC00 NC 4 VCC 5
VCCD C6 0.1uF
9
XTALIN CY7C63723-PC
XTALOUT
DGND LOOP ANTENNA
C7 Y1 26.590MHz C11 AGND U3 1 C12 0.1uF VCCA AGND IN G G G 2 3 4 C13 AGND VCCA C17 0.1uF C14 R7 C18 47pF 0.1uF 0.1uF 36K MC3361-SMD OSC_B OSC_E MIX_OUT LIM_IN DEC_1 DEC_2 QUAD 1 2 3 4 5 6 7 8 OSC_B MIX_IN OSC_E GND MIX_OUT MUTE SCAN_CTL VCC LIM_IN SQUELCH_IN FILTER_OUT DEC_1 FILTER_IN DEC_2 QUAD DEMO_OUT 16 15 14 13 12 11 10 9 AGND AGND WL_DATA SQUELCH R4 R7A1 R5 R6 2K C16 222 Y2 455C28 C19 103 AGND AGND 20pF C10 20pF 0.01UF C8 5pF C9
33pF
10K
VCCA
OUT
1M? 420K
FL1 CFWM455F
5
C15 0.1uF
AGND
Figure 22. Application circuit for RF receiver circuit
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7.6 PCB Layout Consideration
1. Caps for pins 8, 9, 10 MUST have trace lengths LESS than 5mm. 2. The trace lengths of OSCOUT, OSCIN must less than 6mm.
7.7 Recommended Value for R1
Radiometric intensity of LED Bin limits (mW/Sr at 20mA) LED Bin grade Min. N P Q 14.7 17.7 21.2
Typ.
Max. 17.7 21.2 25.4
Note: Tolerance for each bin will be 15% R1 value (ohm), VDD=3.3V LED bin grade Min. N P Q 12 12 12
Typ. 22 22 22
Max.
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8. Package Information 8.1 Package Outline Drawing
20 19 18 17 16 15 14 13 12 11
1
2
3
4
5
6
7
8
9
10
19.30 0.760
3.20 0.126
9.98 0.393
1.02 0.040
5.08 0.200 1.46 0.0575 0.254 0.010
0.457 0.018
1.778 0.070
5 - 12 14.22 0.560
13.589 0.535 11.938 0.470 1 2 3 4 5 6 7 8
5.715 0.225 4.064 0.160 9 10
5.080 0.200
4.55 0.179 20 19 18 17 16 15 14 13 12 11 0.800 0.031
NOTES: 1. All dimensions in MM/INCH. 2. All dimensions tolerance: +/- 0.10mm 3. Maxmumflash: +0.2mm
5.56 0.2189
Figure 23. Package outline drawing
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PixArt Imaging Inc. PAN301BSI-208 CMOS Optical Mouse Sensor
8.2 Recommended PCB Mechanical Cutouts and Spacing
4.064 0.160 2.286 0.090 6.985 0.275 4.445 0.175 1.194 0.047 10.998 0.433 0 ref. 27.153 1.069
16.942 0.667
26.010 1.024
7.544 0.297
0.711 0.028 Optical Center
0 ref.
1.194 0.047 4.445 0.175 6.985 0.275 0.711 0.028
3.251 0.128
7.544 0.297
All Dimensions : mm / inch
Figure 24. Recommended PCB mechanical cutouts and spacing
9. Update History
Version V1.0 Update Creation, Preliminary 1st version 7.1 27MHz RF TX Circuit with Internal Regulator 7.2 27MHz RF TX Circuit with Internal Regulator for Low Power Down Current Date 05/10/2004
V1.1
05/26/2004
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